IQE’s UltraSmooth Strained Silicon breakthrough
 

09 Dec 2004

IQE plc, the leading global outsource supplier of customised epitaxial wafers to the semiconductor industry, today announces a breakthrough in strained silicon technology that potentially opens the way for more rapid deployment of this leading edge technology within the Silicon Industry. Initial device results obtained on IQE Silicon’s proprietary, UltraSmooth Strained Silicon product range, have demonstrated for the first time, a significant enhancement in speed for both nMOS and pMOS devices at sub 100nm Technology Nodes. The results indicate that the smoother surfaces provided by IQEs proprietary strained silicon process lead directly to better pMOS performance.

Many modern day applications use CMOS technologies (Complementary Metal Oxide Silicon) that utilize the properties of both nMOS and pMOS devices. Early work on strained silicon showed that significant enhancement to nMOS devices could be achieved by the introduction of up to 20% germanium to produce tensile strain within a thin “active” strained silicon layer deposited upon the Silicon Gernanium buffer layer. However, the overall impact on device performance was limited as very little enhancement was evident in the performance of pMOS devices. Enhancement to pMOS devices was previously understood to come about only through the introduction of even higher levels of strain by increasing the proportion of germanium in the Silicon Germanium buffer layer. However, the introduction of increased strain results in greater distortion and increased defect levels within the material and an accompanying adverse effect on both nMOS and pMOS device performance. It therefore appeared that further device performance enhancements would be self limiting.

IQE’s approach, for which patent applications have been filed, has been to concentrate on a simple, cost effective, single-stage epitaxial process to produce very low dislocation levels with an “UltraSmooth” strained silicon surface finish. After several months working closely with a major silicon IC manufacturer to assess device performance, the results show that significant performance enhancements to both p-type and n-type devices can be achieved for strained silicon with buffer layers of germanium concentrations as low as 17%.

The high quality of the strained silicon material and performance enhancements achieved using IQE’s proprietary UltraSmooth Strained Silicon have also been confirmed by a number of other major chip manufacturers in Europe, North America and the Far East with whom IQE has been working in close partnership during the last 12 months.

Extensive testing and measurement has demonstrate that IQE’s 17% strained silicon exhibited improvements in mobility (speed) of up to 100% for the nMOS and up to 15% for the pMOS, a much greater mobility/speed enhancement for the pMOS than had previously been achieved for this level of strain, and significantly better than other strained material measured at the same time.

The mobility enhancement of nMOS and pMOS performance is of particular significance, since it should enable the more rapid commercial adoption of strained silicon technology and the scope of IQE’s patent applications covers all key processes for carrier enhancement by the reduction of surface roughness on any form of strained silicon including strained silicon on insulator (sSOI).

Commenting on the results, Dr Drew Nelson, IQE’s CEO said, “We are very encouraged by these excellent initial device results from one of our key development partners, who is a well recognized leading global IC manufacturer. The results are beyond our initial expectations in terms of significant improvements in performance for both nMOS and pMOS mobility, a key development in this exciting new technology. We will continue to work closely with our key partners worldwide to bring this technology to market at the earliest possible opportunity, and the results obtained here represent a key milestone in achieving that goal.”



Contacts:

IQE plc:
Dr Drew Nelson
Chris Meadows
Tel: +44 (0) 29 2083 9400

Buchanan Communications:
Nicola Cronk
Tel: 020 7466 5000



Sales Enquiries:

Alistair Hoy
Sales Manager
IQE Silicon Compounds
Cypress Drive, St Mellons
Cardiff. CF8 OEG

Tele : +44 (0) 2920 837 500
Fax : +44 (0) 2920 837 501
Email : ahoy@iqep.com
Website : www.iqep.com



NOTE TO EDITORS:

About IQE Silicon:
IQE Silicon Compounds Ltd is a wholly owned subsidiary of IQE plc, the leading global outsource supplier of advanced epiwafers to the Semiconductor Industry with manufacturing operations in the U.K. and U.S.A. The Silicon Compounds division was established in 2000 in Cardiff, U.K. and offers fully flexible, dedicated outsource services for silicon-based epitaxial structures. In addition to the range of state-of-the-art CVD epitaxial deposition reactors, the facility in Cardiff includes a class 1 cleanroom equipped with the very latest in wafer preparation and characterization tools. The Silicon Compounds business unit focuses on providing a high-quality, sub-contract epitaxial deposition service, specializing in high-technology inter-layer epitaxial films, including Silicon Germanium (SiGe) and high-end Bi-CMOS semiconductor processes.

 

Glossary of terms:

CMOS:
Complementary metal oxide semiconductor chips (CMOS) use both nMOS (negative) and pMOS (positive) devices. The circuits are designed so that only the positive or the negative device is on at any one time which significantly reduces the power requirements of CMOS chips compared with chips using just one type of transistor (eg Bi-Polar). The lower power consumption of CMOS devices makes them particularly suitable for use in battery-powered devices, such as portable computers.

Epitaxy:
Epitaxial growth is the process by which thin layer of single-crystal material is deposited on single-crystal substrate in a way that the crystallographic structure of the deposited material is the same as that of the substrate.

nMOS:
Negative-channel metal-oxide semiconductors are negatively charged devices (transistors) that are turned on or off by the movement of electrons.

Parasitic Overlap Capacitance (Cov):
Overlap Capacitance is an undesirable effect that is often created when two different layers overlap one another.

pMOS:
Positive-channel metal-oxide semiconductors are positively charged devices that rely on the movement of “holes” (gaps where electrons should be). Because “holes” move slower than electrons, nMOS devices tend to operate faster than pMOS devices.

Sub 100 micron:
“Technology Node” where the gate length (active device dimension) is less than 100nm or one-thousandth’s the diameter of a typical human hair.

Threshold Voltage (Vt):
Threshold Voltage is the voltage needed to be applied to the gate of a metal-oxide semiconductor field effect transistor (MOSFET) in order that an inversion layer is formed at the semiconductor surface.to create a conductive channel between the source and the drain.

Transconductance:
Transconductance is a measure of the performance of a transistor and is generally directly proportional to the gain of the device. For a Field Effect Transistor (FET) the transconductance is the ratio of the change in drain current to the change in gate voltage over a small, defined time interval..